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ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER FEATURES * 10 differential 2.5V/3.3V LVPECL / ECL outputs * 2 selectable differential input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: 3.2GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * Output skew: 25ps (typical) * Part-to-part skew: 85ps (typical) * Propagation delay: 680ps (typical) * Jitter, RMS: < 0.03ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant GENERAL DESCRIPTION The ICS853111-02 is a low skew, high performance 1 - t o - 10 Differential-to-2.5V/3.3V HiPerClockSTM LVPECL/ECL Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS853111-02 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-part skew characteristics make the ICS85311102 ideal for those clock distribution applications demanding well defined perfor mance and repeatability. ICS BLOCK DIAGRAM PCLK0 nPCLK0 PCLK1 nPCLK1 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 CLK_SEL Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9 PIN ASSIGNMENT nQ3 nQ4 nQ5 nQ6 Q3 Q4 Q5 Q6 24 23 22 21 20 19 18 17 VCCO nQ2 Q2 nQ1 Q1 nQ0 Q0 VCCO 25 26 27 28 29 30 31 32 1 VCC 16 15 14 VCCO Q7 nQ7 Q8 nQ8 Q9 nQ9 VCCO ICS853111-02 13 12 11 10 9 V BB 2 CLK_SEL 3 PCLK0 4 nPCLK0 5 VBB 6 PCLK1 7 nPCLK1 8 VEE 32-Lead TQFP 7mm x 7mm x 1.0mm package body Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853111AY-02 www.icst.com/products/hiperclocks.html REV. A JUNE 3, 2005 1 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER Type Description Core supply pin. Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Bias voltage. Pulldown Pullup/Pulldown Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Negative supply pin. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5 6 7 8 9, 16, 25, 32 10, 11 12, 13 14, 15 17, 18 19, 20 21, 22 23 , 2 4 26, 27 28, 29 30, 31 Name VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE VCCO nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Output Input Input Power Power Output Output Output Output Output Output Output Output Output Output Pulldown Pulldown Pullup/Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k TABLE 3A. CLOCK INPUT FUNCTION TABLE Inputs PCLKx 0 1 0 1 nPCLKx 1 0 Biased; NOTE 1 Biased; NOTE 1 Outputs Q0:Q9 LOW HIGH LOW HIGH nQ0:Q9 HIGH LOW HIGH LOW Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting TABLE 3B. CONTROL INPUT FUNCTION TABLE Inputs CLK_SEL 0 1 Selected Source PCLK0, nPCLK0 PCLK1, nPCLK1 Biased; 0 HIGH LOW Single Ended to Differential Inver ting NOTE 1 Biased; 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1 NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". 853111AY-02 www.icst.com/products/hiperclocks.html 2 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to VCC + 0.5 V cations only. Functional operation of product at 0.5V to VEE - 0.5V these conditions or any conditions beyond those 50mA 100mA 0.5mA -65C to 150C 49.5C/W (0 lfpm) listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA (Junction-to-Ambient) Operating Temperature Range, TA -40C to +85C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.8V; VEE = 0V Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.8 85 Units V mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 PCLK0, PCLK1 Input High Current nPCLK0, nPCLK1 Input Low Current -40C Min 2.175 1.405 2.075 1.43 1.86 150 1.2 800 Typ 2.275 1.545 Max 2.38 1.68 2.36 1.765 1.98 1200 3.3 150 Min 2.225 1.425 2.075 1.43 1.86 150 1. 2 800 25C Typ 2.295 1.52 Max 2.37 1.615 2.36 1.765 1.98 1200 3.3 150 Min 2.295 1.44 2.075 1.43 1.86 150 1.2 800 85C Typ 2.33 1.535 Max 2.365 1.63 2.36 1.765 1.98 1200 3.3 150 Units V V V V V V V A A PCLK0, PCLK1 -150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. 853111AY-02 www.icst.com/products/hiperclocks.html 3 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER -40C Min 1.375 0.605 1.275 0.63 150 1.2 800 Typ 1.475 0.745 Max 1.58 0.88 1.56 0.965 1200 2.5 150 Min 1.425 0.625 1.275 0.63 150 1.2 800 25C Typ 1.495 0.72 Max 1.57 0.815 1.56 0.965 1200 2.5 150 Min 1.495 0.64 1.275 0.63 150 1.2 800 85C Typ 1.53 0.735 Max 1.565 0.83 -0.8 0.965 1200 2.5 150 TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 PCLK0, PCLK1 Input High Current nPCLK0, nPCLK1 Input Low Current Units V V V V V V A A PCLK0, PCLK1 -150 -150 -150 nPCLK0, nPCLK1 Input and output parameters var y 1:1 with VCC. VEE can var y +0.125V to -1.3V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 -40C Min -1.125 -1.895 -1.225 -1.87 -1.486 150 VEE+1.2V 800 25C Max -0.92 -1.62 -0.94 -1.535 -1.386 1200 0 85C Max -0.93 -1.685 -0.94 -1.535 -1.386 Typ -1.025 -1.755 Min -1.075 -1.875 -1.225 -1.87 -1.486 150 VEE+1.2V Typ -1.005 -1.78 Min -1.005 -1.86 -1.225 -1.87 -1.486 150 VEE+1.2V Typ -0.97 -1.765 Max -0.935 -1.67 -0.94 -1.535 -1.386 Units V V V V V V V 800 1200 0 800 1200 0 150 150 150 A A Input PCLK0, PCLK1 -150 -150 -150 Low Current nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. 853111AY-02 www.icst.com/products/hiperclocks.html 4 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER -40C Min 600 Typ 680 25 85 0.03 60 200 325 100 Max 3.2 750 37 225 650 725 25 85 0.03 200 280 130 Min 25C Typ Max 3.2 790 37 225 690 790 25 85 0.03 200 270 Min 85C Typ Max 3.2 890 37 225 TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time 20% to 80% Units GHz ps ps ps ps ps tPD tsk(o) tsk(pp) tjit tR/tF All parameters are measured 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 853111AY-02 www.icst.com/products/hiperclocks.html 5 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 -30 -40 -50 the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter at 155.52MHz = 0.03ps (typical) SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 853111AY-02 www.icst.com/products/hiperclocks.html 6 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCC, VCCO = 2V VCC Qx SCOPE nCLK0, nCLK1 LVPECL nQx CLK0, CLK1 V PP Cross Points V CMR V EE VEE = -0.375V to -1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQy PART 2 Qy tsk(pp) nQx Qx nQy Qy tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK0, nCLK1 80% Clock Outputs 80% VSW I N G CLK0, CLK1 nQ0:nQ9 Q0:Q9 tPD 20% tR tF 20% OUTPUT RISE/FALL TIME 853111AY-02 PROPAGATION DELAY www.icst.com/products/hiperclocks.html 7 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS Figure 2A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 2A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS Figure 2B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VDD(or VCC) CLK_IN + VBB - C1 0.1uF FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT 853111AY-02 www.icst.com/products/hiperclocks.html 8 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive Zo = 50 FOUT FIN 125 Zo = 50 FOUT 50 50 VCC - 2V RTT 125 Zo = 50 FIN RTT = 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o Zo = 50 84 84 FIGURE 3A. LVPECL OUTPUT TERMINATION FIGURE 3B. LVPECL OUTPUT TERMINATION 853111AY-02 www.icst.com/products/hiperclocks.html 9 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to 2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 R3 18 FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE 853111AY-02 www.icst.com/products/hiperclocks.html 10 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 60 Ohm 2.5V 2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120 R2 50 Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 R2 120 FIGURE 5A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER FIGURE 5B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1 3.3V 3.3V R4 125 R3 1K R4 1K PCLK nPCLK HiPerClockS Input HiPerClockS PC L K/n PCL K R1 1K R2 1K FIGURE 5C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 5D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK R5 100 - 200 R6 100 - 200 R1 125 R2 125 FIGURE 5E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 853111AY-02 www.icst.com/products/hiperclocks.html 11 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ample, the input is driven by an LVPECL driver. CLK_SEL is set at logic high to select PCLK0/nPCLK0 input. Zo = 50 + SCHEMATIC EXAMPLE This application note provides general design guide using ICS853111-02 LVPECL buffer. Figure 6 shows a schematic example of the ICS853111-02 LVPECL clock buffer. In this ex- Zo = 50 - VCC R2 50 R1 50 VCC C6 (Option) 0.1u R3 50 Zo = 50 Ohm Zo = 50 Ohm 3.3V LVPECL R9 50 C8 (Option) 0.1u R10 50 R11 50 R4 1K 1 2 3 4 5 6 7 8 VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO 32 31 30 29 28 27 26 25 VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 24 23 22 21 20 19 18 17 U1 ICS853111 VCC Zo = 50 + VCC=3.3V Zo = 50 - (U1-9) VCC (U1-16) (U1-25) (U1-32) (U1-1) R8 50 R7 50 C1 0.1uF C2 0.1uF C3 0.1uF C4 0.1uF C5 0.1uF C7 (Option) 0.1u R13 50 FIGURE 6. EXAMPLE ICS853111-02 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC THERMAL RELEASE PATH The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through SOLDER MASK SIGNAL TRACE solder as shown in Figure 7. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. EXPOSED PAD SOLDER SIGNAL TRACE GROUND PLANE 9 10 11 12 13 14 15 16 THERM AL VIA Expose M etal Pad (GROUND PAD) FIGURE 7. P.C. BOARD 853111AY-02 FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE REV. A JUNE 3, 2005 www.icst.com/products/hiperclocks.html 12 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853111-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853111-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 85mA = 323mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW Total Power_MAX (3.8V, with all outputs switching) = 323mW + 309.4mW = 632.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.8C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.632W * 43.8C/W = 112.7C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 32-PIN TQFP, E-PAD, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 69.3C/W 49.5C/W 200 57.8C/W 43.8C/W 500 52.1C/W 41.3C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 853111AY-02 www.icst.com/products/hiperclocks.html 13 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. 3. Calculations and Equations. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER LVPECL output driver circuit and termination are shown in Figure 8. VCCO Q1 VOUT RL 50 VCCO - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CCO * For logic high, VOUT = V (V CC_MAX OH_MAX =V CCO_MAX - 0.935V -V OH_MAX ) = 0.935V =V - 1.67V * For logic low, VOUT = V (V CCO_MAX OL_MAX CCO_MAX -V OL_MAX ) = 1.67V Pd_H = [(V OH_MAX - (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OH_MAX ) = [(2V - (V CCO _MAX -V OH_MAX ))/R ] * (V L CCO _MAX -V OH_MAX )= [(2V - 0.935V)/50] * 0.935V = 19.92mW Pd_L = [(V OL_MAX - (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 853111AY-02 www.icst.com/products/hiperclocks.html 14 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD by Velocity (Linear Feet per Minute) JA 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 69.3C/W 49.5C/W 200 57.8C/W 43.8C/W 500 52.1C/W 41.3C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853111-02 is: 1340 Pin compatible with MC100EP111 and MC100LVEP111 853111AY-02 www.icst.com/products/hiperclocks.html 15 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER FOR TQFP PACKAGE OUTLINE - Y SUFFIX 32 LEAD TQFP, E-PAD -HD VERSION HEAT SLUG DOWN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS ABA-HD SYMBOL N A A1 A2 b c D D1 D2 D3 E E1 E2 E3 e L ccc 0.45 0 --0.05 0.95 0.30 0.09 MINIMUM NOMINAL 32 -0.10 1.0 0.35 -9.00 BASIC 7.00 BASIC 5.60 Ref. 4.00 BASIC 9.00 BASIC 7.00 BASIC 5.60 Ref. 4.00 BASIC 0.80 BASIC 0.60 --0.75 7 0.10 1.20 0.15 1.05 0.40 0.20 MAXIMUM Reference Document: JEDEC Publication 95, MS-026 853111AY-02 www.icst.com/products/hiperclocks.html 16 REV. A JUNE 3, 2005 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER Marking Package 32 lead, E-Pad TQFP 32 lead, E-Pad TQFP 32 lead "Lead-Free," E-Pad TQFP 32 lead "Lead-Free," E-Pad TQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C TABLE 9. ORDERING INFORMATION Part/Order Number ICS853111AY-02 ICS853111AY-02T ICS853111AY-02LF ICS853111AY-02LFT ICS853111A02 ICS853111A02 TBD TBD NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853111AY-02 www.icst.com/products/hiperclocks.html 17 REV. A JUNE 3, 2005 |
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